RF-ICs used in mobile telephones and wireless LANs are still expected to grow at a high rate. At present, tendency of development of the RF-ICs is moving to one chip configuration with a base band IC. According to requirements by the base band IC having an increasing integration degree, development of the RF-ICs using miniaturized CMOS process is necessary. If miniaturization is advanced, elements fluctuation, increase of a consumption current of an analog circuit caused by increase of gate capacity and increase of an area become problems. As a countermeasure, there is an idea that the analog circuit is replaced with a digital circuit.
The present inventors focus on a TDC (Time to Digital Converter) converting a phase difference (time difference) into digital in a technique of an ADPLL.
Note that, as for techniques related to the ADPLL, there are techniques disclosed in U.S. Pat. No. 7,123,102 (Patent Document 1), U.S. Patent Application Publication No. 2005/0116258 (Patent Document 2), J. Lin, “A PVT tolerant 0.18 MHz to 600 MHz self-calibrated digital PLL in 90 nm CMOS process”, ISSCC, February, 2004 (Non-Patent Document 1), T. Olsson, “A Digitally Controlled PLL for SoC Applications, IEEE JOURNAL OF SOLID-STATE CIRCUITS”, May, 2004 (Non-Patent Document 2), T. Watanabe, “An All-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, February, 2003 (Non-Patent Document 3), and T. A. D. Riley, “A Simplified Continuous Phase Modulator Technique”, IEEE TRANSACTIONS ON CIRCUIT AND SYSTEMS II: ANALOG AND DIGITAL SIGNAL PROCESSING, Vol. 41, No. 5, May, 1994 (Non-Patent Document 4). Patent Document 1 relates to automatic band selection of a VCO having a plurality of oscillation bands. Patent Document 2 relates to a dual modulus prescaler. Non-Patent Documents 1 to 3 relate to conventional arts of the TDC. Non-Patent Document 4 relates to a technique superimposing phase modulation on a fractional PLL.